NanoYield™ is an unique design-for-yield platform that for the first time integrates all the key components from one vendor, including advanced device modeling, parallel SPICE simulation engine and hardware-validated statistical analysis algorithms.
NanoYield significantly speeds up the statistical circuit analysis with its superior parallelization technology, highly efficient and accurate statistical algorithms, enabling designers to run yield predication and yield-PPA trade-off for memory, digital and analog circuits. ProPlus offers an integrated GUI-based DFY environment – Nano Design Environment (NDE), to help designers to run variation analysis, predict yield, and guide their designs for optimum yield and PPA.
Full integration: advanced modeling, built-in SPICE engine and high efficient statistical algorithms
Superior speed: fast PVT-3-20X; fast Monte Carlo - 10-100X+; advanced High Sigma-103-105X+
Scalable parallelization: near-linear scaling on private farm or public cloud
High accuracy: silicon validation at 40nm, 28nm & 14nm
Simplified licensing: most economic parallelization licensing model
4-7σ yield analysis for memory and standard cell designs
Fast Monte Carlo analysis for analog and digital block designs
Fast PVT analysis for analog and digital block designs
Supports Hspice and Spectre netlist formats
Full SPICE analysis features (same as NanoSpice)
Full SPICE model support (same as NanoSpice)
Full PVT and fast PVT analysis
Monte Carlo analysis
High Sigma analysis (4-7σ+): 20K+ variables
System High Sigma analysis for full chip yield analysis
Rich yield prediction and statistical circuit analysis functions, e.g., sensitivity analysis, parameter sweeping, etc.
Powerful GUI-based circuit analysis features through Nano Design Environment
64bit Linux OS: Red Hat, CentOS
Multi-core server or computer farm